As semiconductor devices continue to decrease in size, optimal device operation becomes more difficult to achieve. For example, when scaling advanced bipolar transistors two factors are of primary importance: 1) scaling the vertical emitter-base-collector dimension to improve cutoff frequency (Ft) and DC current gain (β), and 2) scaling the lateral dimension of the bipolar transistor to improve the maximum frequency of unity power gain (Fmax) and the RF noise figure (Nfmin). In bipolar transistors, lateral scaling has typically focused on reducing the parasitic extrinsic base resistance (Rbx) and extrinsic base-collector capacitance (CBC).
In order to reduce the extrinsic base-collector capacitance, “raised base” techniques have been used. Over the last decade, conventional raised base techniques have utilized processes having a separate deposition step for creating an epitaxially grown extrinsic base region that connects the single-crystal intrinsic base region to the base contact. In a typical raised base scheme the raised extrinsic base material is silicon (Si), and preferably polysilicon. Consequently, the size of conventionally formed bipolar transistors is limited by the physical properties of the epitaxial silicon raised extrinsic base. Moreover, fabrication of a silicon raised base often significantly increases manufacturing costs, and requires high temperature processing and is accompanied by difficulty in etching and forming the silicon raised base due to low etchant selectivity during fabrication.